Designing embedded systems has become a complex and expensive task, and simulation and other analysis tools are taking on a bigger role in the overall design process. In an effort to speed up the design process, we present an algorithm for reducing the simulation time of large, complex models by creating a parallel schedule from a flattened set of equations that collectively capture the system behavior. The developed approach is applied to a multi-core desktop processor to determine the estimated speedup in a set of subsystem models.